Language

Contract Hardware Engineer Mid.

ASIC
Continuous Improvement
VHDL
FPGA
Field Programmable Gate Array
Application-Specific Integrated Circuit
Project Design
Technical Leadership
UNIX
Subversion
Git
Scripting
Coding
System Integration
PERL
C/C++
Description:

Magnit Global is a leading, global professional services and technology company and a certified “Great Place to Work”. We have been a leader in contingent workforce management since 1991 and work with leading Fortune 500 companies and other large organizations across numerous verticals including consumer electronics, research and development, pharmaceuticals, health services, and many more! 

We're glad to continue a relationship with you and happy to assist in the next steps of your career once more! 

This contract opportunity is with Arrow Electronics. 

About The Role:

Contract Hardware Engineer Mid. will contribute to engineering estimates for new program pursuits. You will require to recommend new tools and practices for continuous improvement in the group's ASIC/FPGA design flow.

What Will You Do:

•    Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration  
•    Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow 
•    Contribute to engineering estimates for new program pursuits. 
•    May provide technical leadership for project design teams by breaking down work, planning activities, and reporting status.

What Will You Need
•    RTL coding and simulation in VHDL/Veriog.     
•    Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure               
•    Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools)       
•    Git, Subversion     
•    Experience with Unix, scripting, C/C++, and/or Perl
•    Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog).
•    ASIC / FPGA lab validation with advanced lab equipment  
•    Design for Test (DFT) and manufacturability issues 
•    Experience with Unix, scripting, C/C++, and/or Perl
Any special or skills related notes:
•    Ability to work with minimal supervision, team with engineers of a variety of skills and backgrounds, and matrix into projects with aggressive schedules and frequent milestones 
•   Strong oral and written communication skills with the ability to document and present one's work and status.
•   Due to nature of the project, U.S. Citizenship is must for this role, please do mention on top of resume if candidate have Active security clearance or not.
•   CW will work onsite from day one at Cedar Rapids, IA (5 days onsite)
•   Experience range - 6-15 years
•    Bachelor of Engineering 


This is the pay range that Magnit reasonably expects to pay for this position: $53.57/hour - $71.43/hour

Benefits: Medical, Dental, Vision, 401K

QUALIFICATION/ LICENSURE :
  • Work Authorization : US Citizen
  • Preferred years of experience : 6+ Years
  • Travel Required : No travel required
  • Shift timings: Not specified
Job Location Cedar Rapids, Iowa
Pay USD 53.57 - USD 71.43 Per Hour
Contract Duration 12 month(s)